In the field of bulk MEMS, deep holes or grooves are formed in a silicon wafer in order to develop functions. Because the silicon wafer which is used at this time is mainly used for supplying semiconductors such as memory or processors etc, a (100) orientated silicon wafer is often used.
In the case of forming deep holes or grooves in a plane direction (100) silicon wafer, it is easy for the wafer to fracture when there are scratches etc due to the properties of the silicon wafer. As an example whereby the easy to fracture properties of the silicon wafer are utilized a technique which makes a silicon wafer easy to fracture by forming a chip separation groove along a cleavage plane is disclosed in Japanese Laid Open Patent H8-139339. However, this ease of fracturing has demerits in terms of handling a pattern formed silicon wafer.
For example, a silicon wafer sometimes fractures even in the case of forming a film using a material with a high level of stress on the silicon wafer. This type of fracture occurs on a cleavage plane in a plane direction <110>.
For example, a technique is disclosed in Japanese Laid Open Patent 2004-349550 in which two silicon wafers are reinforced by mutually misaligning the cleavage planes and joining them together against the properties of a silicon wafer which is easy to fracture along a cleavage plane. However, while combining two silicon wafers secures strength across the entire device, because sufficient strength can not be secured in one silicon wafer, fractures caused by stress in the material which is used in forming a film can not be prevented.
In particular, in the filed of bulk MEMS, the same pattern is often formed a plurality of times having deep holes or grooves along a cleavage plane of a silicon wafer compared to a semiconductor element such as memory. Because the depth of the formed holes or grooves is between a few tens of μm to a few hundred μm, it is easy for fractures to occur along the cleavage plane of the silicon wafer. As a result, when forming the same pattern a plurality of times on a silicon wafer, a pattern arrangement method is preferred in which it is difficult to produce fractures.